(1) Field of the Invention
This invention relates generally to the field of integrated circuits (ICs) fabrication, and more particularly, to a process of forming non-silicide electrostatic discharge (ESD) protection circuit with reduced number of masks and lithography steps.
(2) Description of the Prior Art
The input signals to a metal-oxide-semiconductor (MOS) IC are fed to the gates of MOS transistors. If the voltage applied to the gate oxide insulator becomes excessive, the gate oxide can break down. The dielectric breakdown strength of SiO.sub.2 is approximately 8.times.10.sup.6 V/cm; thus, a 150 .ANG. gate oxide will not tolerate voltages greater than 12V without breaking down. Although this is well in excess of the normal operating voltages of 5V integrated circuits, voltages higher than this may be impressed upon the inputs to the circuits during either human-operator or mechanical handling operations. Please see references such as "Silicon Processing for the VLSI ERA, Volume 2" by Wolf, 1990 (the entire disclosure of which is herein incorporated by reference).
The main source of such voltages is triboelectricity (electricity caused when two materials are rubbed together). A person can develop very high static voltage (i.e., a few hundred to a few thousand volts) simply by walking across a room or by removing an integrated circuit from its plastic package, even when careful handling procedures are followed. If such a high voltage is accidentally applied to the pins of an IC package, its discharge (referred to as electrostatic discharge, or ESD) can cause breakdown of the gate oxide of the devices to which it is applied. The breakdown event may cause sufficient damage to produce immediate destruction of the device, or it may weaken the oxide enough that it will fail early in the operating life of the device (and thereby cause device failure).
All pins-of MOS ICs must be provided with protective circuits to prevent such voltages from damaging the MOS gates. The need for such circuits is also mandated by the increasing use of VLSI devices in such high-noise environments as personal computers, automobiles, and manufacturing control systems. These protective circuits, normally placed between the input and output pads on a chip and the transistor gates to which the pads are connected, are designed to begin conducting or to undergo breakdown, thereby providing an electrical path to ground (or to the power-supply rail). Since the breakdown mechanism is designed to be nondestructive, the circuits provide a normally open path that closes only when a high voltage appears at the input or output terminals, harmlessly discharging the node to which it is connected.
In recent years, the sizes of the MOS transistors have become continuously smaller so that the packing densities of these IC devices have increased considerably. As the sizes of the capacitors become smaller, so as the resistance values of the MOS transistors are increasing, that reduces the operational speed of the IC devices, causing performance problems. Therefore, so-called salicide process has been developed to reduce the resistance of the MOS transistors. Unfortunately, the salicide process will reduce the capacity of the ESD protection circuit.
In order to solve such a problem, an ESD protection circuit without salicide that is incorporated with MOS transistors with salicide has been proposed. Referring now to FIGS. 1A-1H, the conventional fabrication method of an ESD protection circuit without salicide formation is depicted.
First, the process before gate patterning is similar to a typical MOS fabrication process, which includes well and isolation 3 formations on a semiconductor substrate 1, device regions and ESD circuit regions definition on the semiconductor substrate 1, threshold voltage (V.sub.th) adjust implantation, gate oxide 3 growth, polysilicon 5 deposition and gate patterning. The cross-sectional view of the semiconductor substrate 1 after gate patterning is shown in FIG. 1A.
Then, after gate patterning, a first photoresist pattern 9 is created to mask areas other than ESD devices. The high dosage implantation 11 for ESD protection is processed to form heavily doped source/drain regions 13 for ESD protection circuit as shown in FIG. 1B.
Next, PMOS area is then masked by a second photoresist pattern 15 and N type lightly doped drain (NLDD) implantation 17 is performed to form NLDDs 19 as shown in FIG. 1C. Then NMOS is masked by a third photoresist pattern 15 and PLDD 25 is implanted 23 as shown in FIG. 1D.
Then, sidewall spacers 27 are formed by depositing and etching an oxide layer as shown in FIG. 1E. N.sup.+ /P.sup.+ implantations are then performed by masking related areas to form N.sup.+ /P.sup.+ source/drain regions 20, 26, respectively. The cross-sectional view of the semiconductor substrate 1 after N.sup.+ /P.sup.+ implantation is shown in FIG. 1F.
Next, cap oxide layer 29 is then formed over the entire semiconductor substrate 1 surface, followed by one extra fourth photoresist mask 31 (here we call this mask as SAB, standing for salicide blocking) to define non-salicide areas and subsequent oxide etching as shown in FIG. 1G. The masking area depends on necessity. For example, if the gate of the ESD circuit needs to remain salicided, then the gate are would be exposed for further salicidation. The distance between masking edge and gate edge also depends on ESD requirements. It is depicted as FIG. 1G.
Finally, salicidation is then performed on exposed area such as gates, sources/drains of NMOS and PMOS regions to form a metal silicide layer 33 shown in FIG. 1H. Subsequent processes are interlayer dielectric (ILD) oxide cap, contact opening and metal wiring (not shown in the figures). The conventional fabrication method of an ESD protection circuit without salicide formation is now completed.
As stated above, there are many drawbacks of the conventional ESD protection circuit fabrication process:
1. The numerous process steps from ESD implantation toward salicidation, which includes four masks (ESD, N.sup.+, P.sup.+ and SAB) and six lithography steps increase the possibility of wafer contamination.
2. It also takes longer time to fabricate the ESD protection circuit that increases the production cost as well.